`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    15:53:32 03/08/2022 
// Design Name: 
// Module Name:    control 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
`include "define.v"
module control(
					//input [3:0] KYPD_ROW,
					//output [3:0] KYPD_COL,
					input Clock,
					input  [4:0] Switch , 
					input rst,
					output [6:0] Segs ,   
					output  [5:0]   En,
					output [7:0]ClkCnt);      
					wire counter;
					wire mips_counter;
					wire [31:0]data;
					wire [3:0] num;
					wire regEn;
					assign ClkCnt = clkcnt;
					reg[7:0]clkcnt=8'b0;
					
					always@(posedge mips_counter)begin
						clkcnt<=clkcnt+1;
					end
					
					clock _clock(.Reset(1'b0),.Clock(Clock),.DividedClock(counter),.MIPSClock(mips_counter));
					
					//assign En = ~Btn0 ; // Btn0 means for Disable   
					display _display(.Data(data[23:0]),.Clock(counter),.Reset(1'b0),.Enable(En),.Num(num),.En(regEn)     );
					regs _regs( .digit(num) ,.enable(regEn) , .out_regs(Segs) );
					
					wire[`InstAddrBus] inst_addr;
					 wire[`InstBus] inst;
					 wire rom_ce;
					 
					 openmips openmips0(
						.clk(mips_counter),.rst(rst),
						.rom_addr_o(inst_addr),.rom_data_i(inst),
						.rom_ce_o(rom_ce),
						.switch(Switch),
						.data(data)
					 );
					 
					 inst_rom inst_rom0(
						.ce(rom_ce),
						.addr(inst_addr),.inst(inst)
					 );
					//assign data[3:0] = KYPD_ROW;
					//keypad _keypad(.CLK(counter),.ROW(KYPD_ROW),.COL(KYPD_COL),.DATA(data[3:0]));

endmodule
